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Macros</h2></td></tr>
<tr class="memitem:ga51a9fc13b8a6a270b1a1c531f54dcd8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__osd__v4__0.html#ga51a9fc13b8a6a270b1a1c531f54dcd8a">XOSD_HW_H_</a></td></tr>
<tr class="separator:ga51a9fc13b8a6a270b1a1c531f54dcd8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Offsets</div></td></tr>
<tr class="memitem:ga391290622b578053a6e4f87b94afe6d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__osd__v4__0.html#ga391290622b578053a6e4f87b94afe6d2">XOSD_ISR_OFFSET</a>&#160;&#160;&#160;<a class="el" href="group__osd__v4__0.html#gaee8b66db164a6929f9d75c1e75b6c4f7">XOSD_STATUS_OFFSET</a></td></tr>
<tr class="separator:ga391290622b578053a6e4f87b94afe6d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Memory footprint of layers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Graphics Controller Bank related constants</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Active Size Register bit definition and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Background Color Channel 0 Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Background Color Channel 1 Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Background Color Channel 2 Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Maximum number of the layers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Layer Control (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) bit</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>definition and Shifts </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Layer Position (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) bit</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>definition and Shifts </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Layer Size (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) bit</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>definition and Shift </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Graphics Controller Write Bank Address bit definition and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Graphics Controller Active Bank Address bit definition and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Version Register bit definition and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Software Reset</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Register Bit Masks. It is applicable for ISR and IER.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Layer Types</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Supported instruction numbers given an instruction memory size</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC instruction word offset definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC Instruction word 0 definition and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC Instruction word 1 definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC Instruction word 2 definition and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC Instruction word 3 definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC Instruction Operation Code definition (used in Instruction word 0)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC color size</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GC font unit size</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Layer priority</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Output Encoding Register bit definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error Register bit definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register bit definition</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Constants. It is defined as constants to use instead magic numbers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Compatibility Macros</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Core register I/O APIs</div></td></tr>
<tr class="memitem:ga09c0fe42f0cb0fe4a84e84acb6d548f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__osd__v4__0.html#ga09c0fe42f0cb0fe4a84e84acb6d548f3">XOsd_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XOsd_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
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<tr class="memitem:ga37791d01d7ba72baa57bd45c2744a6b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__osd__v4__0.html#ga37791d01d7ba72baa57bd45c2744a6b7">XOsd_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;XOsd_Out32((BaseAddress) + (u32)(RegOffset), (Data))</td></tr>
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